The present invention relates to semiconductor devices and the fabrication method thereof, and particularly a semiconductor device having a ferroelectric capacitor and the fabrication method thereof.
With the demand of higher integration density, FeRAM devices constituting a ferroelectric memory are also subjected to the demand of further miniaturization. In relation to this, efforts are being made on the development of the FeRAM device having a stacked structure in place of the planar structure (Reference should be made to Patent Reference 1 or 2, for example). In realizing a stacked structure, an approach of etching the lower electrode film, the ferroelectric film and the upper electrode film in one step at the time of forming the capacitor part of the ferroelectric memory cell has been used for the purpose of higher integration density (Reference should be made to Patent Reference 2).
FIG. 1 is an example of the 1T1C stacked type ferroelectric memory proposed in the Japanese Patent Application 2002-249448 filed by the same applicant as the present patent application. In this example, too, a lower electrode film 111, a ferroelectric film 112 and an upper electrode film 113 are formed, and then, all these three layers are etched in one step to form a ferroelectric capacitor 101 of the stacked type over the MOS transistor Tr. Here, it should be noted that one impurity diffusion region 116 of the MOS transistor Tr is connected electrically to the lower electrode 111 of the ferroelectric capacitor 101 via a conductive plug 105a, while the other impurity diffusion region 116 is connected to a bit line 109 via conductive plugs 105b, 106, 108 and a conductive pad 107. Further, a gate 118 of the MOS transistor Tr forms the wiring of the word line.
In order to improve the surface area utilization efficiency, it is necessary at the time of the one-step patterning of the lower electrode film 111, the ferroelectric film 112 and the upper electrode 113, to carry out the etching with an angle close to the vertical angle. In order to obtain such a capacitor shape characterized by little tapering, it becomes necessary to use a high temperature etching technology that uses a chemical reaction while maintaining the wafer at a high temperature of about 400° C.
Further, there is a need of maintaining near vertical taper angle and further the need of preventing electrical contact between the upper electrode and the lower electrode via sidewall deposits. On the other hand, such various requirements urges the use of advanced etching technology such as the high temperature etching technology. On the other hand, even when such high temperature etching technology is used, it is difficult to form a capacitor free from leakage between the upper electrode and the lower electrode with reliability.
Further, because of the one-step etching applied to the lower electrode film 111, the ferroelectric film 112 and the upper electrode film 113, it should be noted that the sidewall of the ferroelectric film 112 is exposed in each capacitor cell. Although the surface of the patterned capacitor and the substrate surface are covered by a capacitor protection film 104, the use of such a capacitor protection film 104 cannot completely prevent the penetration of water through the protection film 104 and through the sidewall of the ferroelectric capacitor 112 in the processes thereafter conducted in reducing ambient such as a film formation process or thermal annealing process. Thereby, the reducing reaction associated with the penetrated hydrogen molecules causes the problem that the capacitor performance is degraded. In the case PZT family ferroelectrics are used for the material of the ferroelectric capacitor, in particular, the material contains Pb, while Pb easily causes decoupling of oxygen. Thereby, there occurs loss of lead, and severe degradation may be caused.
When such degradation of capacitor is caused, there occurs a reduction of effective area in the final capacitor, contrary to the effort of improving the surface area utilization efficiency by conducting one-step etching with near vertical angle.
After the ferroelectric capacitor 101 is thus formed with the one-step etching, a wiring layer constituting a plate line 103 is needed for interconnecting isolated upper electrodes 113.                Patent Reference 1 Japanese Laid-Open Patent Application 11-97535        Patent Reference 2 Japanese Laid-Open Patent Application 10-308515        